Pilar Parra (Selection)

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7 Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta: Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896

5 Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta: Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449

4 Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia: Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electronics 1(1): 11-19 (2005)

3 Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS 2003: 491-500

2 Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS 2002: 209-218

1 Pilar Parra, Antonio J. Acosta, Manuel Valencia: Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457

Selection of 6 from 7 records - Pilar Parra has 14 coauthors

7		Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta: Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896
5		Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta: Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449
4		Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia: Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electronics 1(1): 11-19 (2005)
3		Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS 2003: 491-500
2		Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS 2002: 209-218
1		Pilar Parra, Antonio J. Acosta, Manuel Valencia: Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457