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Sai Phaneendra P. (Selection)

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3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350

Selection of 3 from 3 records - Sai Phaneendra P. has 8 coauthors

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