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| 6 | Koichi Nose, Takayasu Sakurai: Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29 | |
| 5 | Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai: Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286 | |
| 4 | Koichi Nose, Takayasu Sakurai: Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474 | |
| 3 | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai: Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230 | |
| 2 | Koichi Nose, Takayasu Sakurai: Analysis and future trend of short-circuit power. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1023-1030 (2000) | |
| 1 | Koichi Nose, Takayasu Sakurai: Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326 |
Selection of 6 from 7 records - Koichi Nose has 19 coauthors
Copyright © 2009-12-05 by Michael Ley (ley@uni-trier.de)