Ryo Nemoto (Selection)

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Selection of 5 from 5 records - Ryo Nemoto has 16 coauthors

Last update 2012-09-10 CET by the DBLP Team —

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5		Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura: 10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150
4		Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura: A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. J. Solid-State Circuits 46(12): 3101-3112 (2011)
3		Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito: A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. ISSCC 2010: 368-369
2		Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito: A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. J. Solid-State Circuits 45(12): 2838-2849 (2010)
1		Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito: 10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1^st-order ΔΣ modulator. ISSCC 2009: 186-187