Ashok Narasimhan (Selection)

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6 Ashok Narasimhan, Ramalingam Sridhar: A low power and low area active clock deskewing technique for sub-90nm technologies. SoCC 2008: 179-182

5 Ashok Narasimhan, Ramalingam Sridhar: Impact of Variability on Clock Skew in H-tree Clock Networks. ISQED 2007: 458-466

4 Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar: A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. VLSI Design 2006: 491-494

3 Prachee Sharma, Asheq Khan, Ashok Narasimhan, Ramalingam Sridhar, Satish K. Tripathi: Energy Conservation in Sensor Networks through Selective Node Activation. WOWMOM 2006: 115-124

2 Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar: A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. VLSI Design 2005: 130-133

1 Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar: A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. VLSI Design 2005: 634-639

Selection of 6 from 6 records - Ashok Narasimhan has 8 coauthors

6		Ashok Narasimhan, Ramalingam Sridhar: A low power and low area active clock deskewing technique for sub-90nm technologies. SoCC 2008: 179-182
5		Ashok Narasimhan, Ramalingam Sridhar: Impact of Variability on Clock Skew in H-tree Clock Networks. ISQED 2007: 458-466
4		Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar: A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. VLSI Design 2006: 491-494
3		Prachee Sharma, Asheq Khan, Ashok Narasimhan, Ramalingam Sridhar, Satish K. Tripathi: Energy Conservation in Sensor Networks through Selective Node Activation. WOWMOM 2006: 115-124
2		Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar: A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. VLSI Design 2005: 130-133
1		Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar: A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. VLSI Design 2005: 634-639