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Mitaro Namiki (Selection)

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8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLIppei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo: A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo: Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNorito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323

Selection of 5 from 26 records - Mitaro Namiki has 67 coauthors

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