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Mitaro Namiki (Selection)

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8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLIppei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo: A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo: Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNorito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615

Selection of 8 from 26 records - Mitaro Namiki has 67 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page