James H. Mulligan Jr. (Selection)

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4 Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997)

3 Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751

2 Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486

Selection of 3 from 4 records - James H. Mulligan Jr. has 2 coauthors

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4		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997)
3		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751
2		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486