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| 101 |       | Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr: SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. IJES 3(3): 109-118 (2008) |
| 100 | | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. IJES 3(3): 150-159 (2008) |
| 86 | | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 70 | | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 |
| 63 | | Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 |
| 60 | | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 |
| 59 | | Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 |
| 57 | | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46 |
| 54 | | Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 |
| 52 | | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973 |
| 34 | | Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001) |
Selection of 11 from 145 records - Heinrich Meyr has 159 coauthors
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