Tadayuki Matsumura (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

4 Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406

3 Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI 2008: 447-450

2 Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88

1 Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Transactions 91-A(12): 3576-3584 (2008)

Selection of 4 from 4 records - Tadayuki Matsumura has 10 coauthors

4		Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406
3		Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI 2008: 447-450
2		Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88
1		Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Transactions 91-A(12): 3576-3584 (2008)