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| 2 |       | Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil: A Scalable Symbolic Simulator for Verilog RTL. MTV 2007: 51-59 |
Selection of 1 from 2 records - Kailasnath Maneparambil has 6 coauthors
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