Eduardo R. de Lima (Selection)

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4 Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima: Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. FPL 2004: 494-504

2 Ma José Canet, Felip Vicedo, Vicenc Almenar, Javier Valls, Eduardo R. de Lima: A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC 2004: 531-535

Selection of 2 from 4 records - Eduardo R. de Lima has 5 coauthors

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4		Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima: Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. FPL 2004: 494-504
2		Ma José Canet, Felip Vicedo, Vicenc Almenar, Javier Valls, Eduardo R. de Lima: A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC 2004: 531-535