| 3 |       | Seung-Jun Bae,
Young-Soo Sohn,
Tae-Young Oh,
Si-Hong Kim,
Yun-Seok Yang,
Dae-Hyun Kim,
Sang-Hyup Kwak,
Ho-Seok Seol,
Chang-Ho Shin,
Min-Sang Park,
Gong-Heom Han,
Byeong-Cheol Kim,
Yong-Ki Cho,
Hye-Ran Kim,
Su-Yeon Doo,
Young-Sik Kim,
Dong-Seok Kang,
Young-Ryeol Choi,
Sam-Young Bang,
Sun-Young Park,
Yong-Jae Shin,
Gil-Shin Moon,
Cheol-Goo Park,
Woo-Seop Kim,
Hyang-Ja Yang,
Jeong-Don Lim,
Kwang-Il Park,
Joo-Sun Choi,
Young-Hyun Jun:
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
ISSCC 2011: 498-500 |
| 2 | | Tae-Young Oh,
Young-Soo Sohn,
Seung-Jun Bae,
Min-Sang Park,
Ji-Hoon Lim,
Yong-Ki Cho,
Dae-Hyun Kim,
Dong-Min Kim,
Hye-Ran Kim,
Hyun-Joong Kim,
Jin-Hyun Kim,
Jin-Kook Kim,
Young-Sik Kim,
Byeong-Cheol Kim,
Sang-Hyup Kwak,
Jae-Hyung Lee,
Jae-Young Lee,
Chang-Ho Shin,
Yun-Seok Yang,
Beom-Sig Cho,
Sam-Young Bang,
Hyang-Ja Yang,
Young-Ryeol Choi,
Gil-Shin Moon,
Cheol-Goo Park,
Seokwon Hwang,
Jeong-Don Lim,
Kwang-Il Park,
Joo-Sun Choi,
Young-Hyun Jun:
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
J. Solid-State Circuits 46(1): 107-118 (2011) |
| 1 | | Tae-Young Oh,
Young-Soo Sohn,
Seung-Jun Bae,
Min-Sang Park,
Ji-Hoon Lim,
Yong-Ki Cho,
Dae-Hyun Kim,
Dong-Min Kim,
Hye-Ran Kim,
Hyun-Joong Kim,
Jin-Hyun Kim,
Jin-Kook Kim,
Young-Sik Kim,
Byeong-Cheol Kim,
Sang-Hyup Kwak,
Jae-Hyung Lee,
Jae-Young Lee,
Chang-Ho Shin,
Yun-Seok Yang,
Beom-Sig Cho,
Sam-Young Bang,
Hyang-Ja Yang,
Young-Ryeol Choi,
Gil-Shin Moon,
Cheol-Goo Park,
Seokwon Hwang,
Jeong-Don Lim,
Kwang-Il Park,
Joo-Sun Choi,
Young-Hyun Jun:
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
ISSCC 2010: 434-435 |
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