Daehong Kim (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

7 Daehong Kim, Dongwan Shin, Kiyoung Choi: Pipelining with common operands for power-efficient linear systems. IEEE Trans. VLSI Syst. 13(9): 1023-1034 (2005)

5 Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi: High-level synthesis under multi-cycle interconnect delay. ASP-DAC 2001: 662

4 Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi: Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. ICCAD 2001: 320-

3 Daehong Kim, Dongwan Shin, Kiyoung Choi: Low power pipelining of linear systems: a common operand centric approach. ISLPED 2001: 225-230

2 Youngsoo Shin, Daehong Kim, Kiyoung Choi: Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC 2000: 495-500

1 Daehong Kim, Kiyoung Choi: Power-conscious High Level Synthesis Using Loop Folding. DAC 1997: 441-445

Selection of 6 from 7 records - Daehong Kim has 8 coauthors

7		Daehong Kim, Dongwan Shin, Kiyoung Choi: Pipelining with common operands for power-efficient linear systems. IEEE Trans. VLSI Syst. 13(9): 1023-1034 (2005)
5		Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi: High-level synthesis under multi-cycle interconnect delay. ASP-DAC 2001: 662
4		Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi: Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. ICCAD 2001: 320-
3		Daehong Kim, Dongwan Shin, Kiyoung Choi: Low power pipelining of linear systems: a common operand centric approach. ISLPED 2001: 225-230
2		Youngsoo Shin, Daehong Kim, Kiyoung Choi: Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC 2000: 495-500
1		Daehong Kim, Kiyoung Choi: Power-conscious High Level Synthesis Using Loop Folding. DAC 1997: 441-445