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Ming-Dou Ker (Selection)

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55Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang: On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS 2009: 2281-2284
44Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng: ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. SoCC 2007: 277-280

Selection of 2 from 71 records - Ming-Dou Ker has 70 coauthors

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