Andrew A. Kennings (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

28 Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox: FPGA technology mapping with encoded libraries and staged priority cuts. TRETS 4(4): 35 (2011)

27 Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu: Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL 2010: 532-537

26 Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu: Power minimisation during field programmable gate array placement. IET Computers & Digital Techniques 4(3): 170-183 (2010)

25 Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox: FPGA technology mapping with encoded libraries andstaged priority cuts. FPGA 2009: 143-150

21 Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu, Andrew A. Kennings: A technique for minimizing power during FPGA placement. FPL 2008: 233-238

Selection of 5 from 31 records - Andrew A. Kennings has 30 coauthors

Last update 2012-09-10 CET by the DBLP Team —

Content released under the ODC-BY 1.0 license — See also our legal information page

28		Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox: FPGA technology mapping with encoded libraries and staged priority cuts. TRETS 4(4): 35 (2011)
27		Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu: Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL 2010: 532-537
26		Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu: Power minimisation during field programmable gate array placement. IET Computers & Digital Techniques 4(3): 170-183 (2010)
25		Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox: FPGA technology mapping with encoded libraries andstaged priority cuts. FPGA 2009: 143-150
21		Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu, Andrew A. Kennings: A technique for minimizing power during FPGA placement. FPL 2008: 233-238