Shoji Kawahara (Selection)

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3 Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675

2 Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781

1 Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615

Selection of 3 from 4 records - Shoji Kawahara has 9 coauthors

3		Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675
2		Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
1		Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615