Chandan Karfa (Selection)

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5 Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar: An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008)

4 Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade: Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434

3 Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade: Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140

2 Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78

1 Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146

Selection of 5 from 5 records - Chandan Karfa has 5 coauthors

5		Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar: An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008)
4		Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade: Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434
3		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade: Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140
2		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78
1		Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146