Deepa Kannan (Selection)

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2 Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520

1 Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma Vrudhul: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539

Selection of 2 from 3 records - Deepa Kannan has 8 coauthors

2		Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520
1		Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma Vrudhul: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539