Daher Kaiss (Selection)

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7 Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili: Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26

6 Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18

3 Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65

1 John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143

Selection of 4 from 7 records - Daher Kaiss has 9 coauthors

7		Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili: Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26
6		Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18
3		Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65
1		John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143