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Peter A. Jamieson
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| 20 |       | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson: The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 |
| 19 | | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose: VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. TRETS 4(4): 32 (2011) |
| 11 | | Peter A. Jamieson, Jonathan Rose: Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. VLSI Syst. 18(12): 1696-1709 (2010) |
| 7 | | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose: VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA 2009: 133-142 |
| 5 |  | Peter Jamieson, Jonathan Rose: A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL 2005: 305-310 |
Selection of 5 from 20 records - Peter Jamieson has 33 coauthors
Last update 2012-09-10 CET by the DBLP Team —
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