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Peter A. Jamieson
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| 20 |       | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson: The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 |
Selection of 1 from 20 records - Peter Jamieson has 33 coauthors
Last update 2012-09-10 CET by the DBLP Team —
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