Ghassem Jaberipur (Selection)

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9 Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin: Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. IEEE Trans. Computers 59(5): 694-706 (2010)

6 Ghassem Jaberipur, Behrooz Parhami: Unified Approach to the Design of Modulo-(2ⁿ +/- 1) Adders Based on Signed-LSB Representation of Residues. IEEE Symposium on Computer Arithmetic 2009: 57-64

3 Ghassem Jaberipur, Behrooz Parhami: Constant-time addition with hybrid-redundant numbers: Theory and implementations. Integration 41(1): 49-64 (2008)

1 Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi: An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. VLSI Signal Processing 42(2): 149-158 (2006)

Selection of 4 from 12 records - Ghassem Jaberipur has 5 coauthors

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9		Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin: Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. IEEE Trans. Computers 59(5): 694-706 (2010)
6		Ghassem Jaberipur, Behrooz Parhami: Unified Approach to the Design of Modulo-(2ⁿ +/- 1) Adders Based on Signed-LSB Representation of Residues. IEEE Symposium on Computer Arithmetic 2009: 57-64
3		Ghassem Jaberipur, Behrooz Parhami: Constant-time addition with hybrid-redundant numbers: Theory and implementations. Integration 41(1): 49-64 (2008)
1		Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi: An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. VLSI Signal Processing 42(2): 149-158 (2006)