Masahiko Iwane (Selection)

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8		Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane: An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. ERSA 2009: 233-239
7		Akira Yamawaki, Masahiko Iwane: An intermediate hardware model with load/store unit for C to FPGA. FPGA 2009: 279
6		Akira Yamawaki, Masahiko Iwane: An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. ICPADS 2007: 1-8
5		Akira Yamawaki, Masahiko Iwane: An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. Circuits, Signals, and Systems 2005: 142-147
4		Akira Yamawaki, Masahiko Iwane: Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ISPAN 2005: 324-333
3		Akira Yamawaki, Masahiko Iwane: Evaluation of mechanisms introduced to improve performance of TSVM cache. Parallel and Distributed Computing and Networks 2004: 502-507
2		Akira Yamawaki, Masahiko Iwane: Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. ICPADS 2002: 83-90
1		Masahiko Iwane, Akira Yamawaki, Makoto Tanaka: Tagged communication and synchronization memory for multiprocessor-on-a-chip. Systems and Computers in Japan 32(4): 1-13 (2001)

Selection of 8 from 8 records - Masahiko Iwane has 3 coauthors