Tetsuro Itakura (Selection)

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25 Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura: A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. ISSCC 2012: 248-250

22 Akihide Sai, Takafumi Yamaji, Tetsuro Itakura: A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC 2011: 98-100

10 Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura: A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Transactions 91-A(2): 557-560 (2008)

Selection of 3 from 25 records - Tetsuro Itakura has 39 coauthors

Last update 2012-09-10 CET by the DBLP Team —

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25		Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura: A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. ISSCC 2012: 248-250
22		Akihide Sai, Takafumi Yamaji, Tetsuro Itakura: A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC 2011: 98-100
10		Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura: A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Transactions 91-A(2): 557-560 (2008)