Tetsuya Ichikawa (Selection)

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5 Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Transactions 90-A(1): 160-168 (2007)

4 Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa: Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Transactions 90-A(1): 169-178 (2007)

3 Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: DPA Leakage Models for CMOS Logic Circuits. CHES 2005: 366-382

Selection of 3 from 5 records - Tetsuya Ichikawa has 9 coauthors

5		Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Transactions 90-A(1): 160-168 (2007)
4		Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa: Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Transactions 90-A(1): 169-178 (2007)
3		Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: DPA Leakage Models for CMOS Logic Circuits. CHES 2005: 366-382