Jing-Reng Huang (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

14 Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004)

9 Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193

8 Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322

4 Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281

1 Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)

Selection of 5 from 16 records - Jing-Reng Huang has 29 coauthors

Last update 2012-09-10 CET by the DBLP Team —

Content released under the ODC-BY 1.0 license — See also our legal information page

14		Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004)
9		Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193
8		Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322
4		Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281
1		Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)