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| 124 |       | Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar: Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750 |
| 51 | | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006) |
| 26 | | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 |
| 23 | | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004) |
| 16 | | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003) |
| 15 | | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69 |
| 12 | | Jiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002) |
| 11 | | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 |
| 10 |  | Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483 |
| 9 | | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 |
| 8 | | Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 |
| 7 | | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |
| 6 | | Jiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001) |
| 5 | | Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103 |
| 4 | | Jiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000) |
| 3 | | Jiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89 |
| 2 | | Jiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138 |
| 1 | | Huibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999) |
Selection of 18 from 135 records - Jiang Hu has 111 coauthors
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