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Jiang Hu (Selection)

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127Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu: GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. 16(3): 24 (2011)
126Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Rupesh S. Shelar, Jiang Hu: Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 416-426 (2011)
121Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Yu Yang, Jiang Hu: Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD 2010: 277-283
120Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVenkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li: Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142
113Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu: A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 223-234 (2010)
110Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu: GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946
109Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu: A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD 2009: 27-34
100Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106
98Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu, Weiping Shi: Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22
93Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYifang Liu, Jiang Hu, Weiping Shi: Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008)

Selection of 10 from 135 records - Jiang Hu has 111 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page