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| 115 |       | Shiyan Hu, Patrik Shah, Jiang Hu: Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Trans. VLSI Syst. 18(6): 1002-1006 (2010) |
| 106 | | Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing for Cell-Library-Based Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 818-825 (2009) |
| 105 | | Shiyan Hu, Jiang Hu: A fast general slew constrained minimum cost buffering algorithm. Microelectronics Journal 40(10): 1482-1486 (2009) |
| 86 | | Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852 |
| 85 | | Shiyan Hu, Jiang Hu: Unified adaptivity optimization of clock and logic signals. ICCAD 2007: 125-130 |
| 81 | | Shiyan Hu, Jiang Hu: Pattern sensitive placement for manufacturability. ISPD 2007: 27-34 |
| 80 | | Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi: An Efficient Algorithm for RLC Buffer Insertion. ISQED 2007: 171-175 |
| 75 | | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007) |
| 72 | | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |
| 67 | | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 |
| 66 | | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. DAC 2006: 379-384 |
| 61 | | Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi: A new RLC buffer insertion algorithm. ICCAD 2006: 553-557 |
Selection of 12 from 135 records - Jiang Hu has 111 coauthors
Last update 2012-09-10 CET by the DBLP Team —
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