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Toshinori Hosokawa (Selection)

List of publications from the DBLP Bibliography Server - FAQ
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16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Transactions 87-D(3): 609-619 (2004)
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLToshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara: A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroshi Date, Toshinori Hosokawa, Michiaki Muraoka: A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium 2002: 305-310
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium 2002: 55-60
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS 2002: 328-335

Selection of 6 from 19 records - Toshinori Hosokawa has 29 coauthors

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