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Ziyad Hanna (Selection)

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21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDaher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili: Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLZurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLZurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJohn Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143

Selection of 4 from 24 records - Ziyad Hanna has 26 coauthors

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