Om Prakash Gangwal (Selection)

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12 Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. DATE 2005: 1182-1187

11 Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 4-17 (2005)

10 Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. DATE 2004: 764-769

Selection of 3 from 12 records - Om Prakash Gangwal has 25 coauthors

Last update 2012-09-10 CET by the DBLP Team —

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12		Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. DATE 2005: 1182-1187
11		Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 4-17 (2005)
10		Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. DATE 2004: 764-769