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Masahiro Fujita (Selection)

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224Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasahiro Fujita, Hiroaki Yoshida: Post-silicon patching for verification/debugging with high-level models and programmable logic. ASP-DAC 2012: 232-237
222Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita: On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700
221Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasahiro Fujita, Hiroaki Yoshida: Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). FPGA 2012: 271
211Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroaki Yoshida, Masahiro Fujita: An energy-efficient patchable accelerator for post-silicon engineering changes. CODES+ISSS 2011: 13-20
185Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroaki Yoshida, Masahiro Fujita: Performance-Constrained Transistor Sizing for Different Cell Count Minimization. JIP 18: 252-262 (2010)
177Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroaki Yoshida, Masahiro Fujita: Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. ISQED 2009: 366-370
172Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Transactions 92-A(6): 1464-1475 (2009)
168Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroaki Yoshida, Masahiro Fujita: Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. DATE 2008: 1099-1102
166no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida: A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. ICSOFT (SE/MUSE/GSDCA) 2008: 240-245
103Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita: Simultaneous Circuit Transformation and Routing. VLSI Design 2002: 479-483

Selection of 10 from 224 records - Masahiro Fujita has 247 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page