| 12 |       | Ankur Agrawal,
John F. Bulzacchelli,
Timothy O. Dickson,
Yong Liu,
José A. Tierno,
Daniel J. Friedman:
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
ISSCC 2012: 134-136 |
| 10 | | John F. Bulzacchelli,
Troy J. Beukema,
Daniel Storaska,
Ping-Hsuan Hsieh,
Sergey V. Rylov,
Daniel Furrer,
Daniele Gardellini,
Andrea Prati,
Christian Menolfi,
David Hanson,
Juergen Hertle,
Thomas Morf,
Vivek Sharma,
Ram Kelkar,
Herschel A. Ainspan,
William Kelly,
Glenn Ritter,
Jon Garlett,
Robert Callan,
Thomas Toifl,
Daniel J. Friedman:
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.
ISSCC 2012: 324-326 |
| 9 | | John F. Bulzacchelli,
Zeynep Toprak Deniz,
Todd M. Rasmus,
Joseph A. Iadanza,
William L. Bucossi,
Seongwon Kim,
Rafael Blanco,
Carrie E. Cox,
Mohak Chhabra,
Christopher D. LeBlanc,
Christian L. Trudeau,
Daniel J. Friedman:
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
J. Solid-State Circuits 47(4): 863-874 (2012) |
| 8 | | Timothy O. Dickson,
Yong Liu,
Sergey V. Rylov,
Bing Dang,
Cornelia K. Tsang,
Paul S. Andry,
John F. Bulzacchelli,
Herschel A. Ainspan,
Xiaoxiong Gu,
Lavanya Turlapati,
Michael P. Beakes,
Benjamin D. Parker,
John U. Knickerbocker,
Daniel J. Friedman:
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
J. Solid-State Circuits 47(4): 884-896 (2012) |
| 5 | | Yong Liu,
Byungsub Kim,
Timothy O. Dickson,
John F. Bulzacchelli,
Daniel J. Friedman:
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
ISSCC 2009: 182-183 |
| 4 | | John F. Bulzacchelli,
Timothy O. Dickson,
Zeynep Toprak Deniz,
Herschel A. Ainspan,
Benjamin D. Parker,
Michael P. Beakes,
Sergey V. Rylov,
Daniel J. Friedman:
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
ISSCC 2009: 368-369 |
| 3 | | Alexander Rylyakov,
José A. Tierno,
Herschel A. Ainspan,
Jean-Olivier Plouchart,
John F. Bulzacchelli,
Zeynep Toprak Deniz,
Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
ISSCC 2009: 94-95 |
Selection of 7 from 12 records - Daniel J. Friedman has 66 coauthors
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