Marius Evers (Selection)

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7 Jared Stark, Marius Evers, Yale N. Patt: Variable Length Path Branch Prediction. ASPLOS 1998: 170-179

6 Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271

5 Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61

4 Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. International Journal of Parallel Programming 26(4): 449-478 (1998)

3 Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997)

2 Marius Evers, Po-Yung Chang, Yale N. Patt: Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA 1996: 3-11

1 Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO 1996: 191-200

Selection of 7 from 8 records - Marius Evers has 10 coauthors

7		Jared Stark, Marius Evers, Yale N. Patt: Variable Length Path Branch Prediction. ASPLOS 1998: 170-179
6		Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271
5		Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61
4		Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. International Journal of Parallel Programming 26(4): 449-478 (1998)
3		Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997)
2		Marius Evers, Po-Yung Chang, Yale N. Patt: Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA 1996: 3-11
1		Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO 1996: 191-200