Sreeram Duvvuru (Selection)

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2 Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162

1 Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180

Selection of 2 from 2 records - Sreeram Duvvuru has 2 coauthors

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2		Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162
1		Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180