Prashant Dubey (Selection)

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5		Akhil Garg, Prashant Dubey: On Chip Jitter Measurement through a High Accuracy TDC. ISQED 2008: 844-847
4		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Built in Defect Prognosis for Embedded Memories. DDECS 2007: 167-172
3		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: GALS Based Shared Test Architecture for Embedded Memories. ISCAS 2007: 157-160
2		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI 2007: 171-178
1		Akhil Garg, Prashant Dubey: Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT 2006: 166-174

Selection of 5 from 5 records - Prashant Dubey has 2 coauthors