Mindaugas Drazdziulis (Selection)

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6 Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256

5 Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191

3 Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563

Selection of 3 from 6 records - Mindaugas Drazdziulis has 6 coauthors

6		Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256
5		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191
3		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563