Sheng Chou (Selection)

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2 Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho: An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1045-1057 (2011)

Selection of 1 from 4 records - Sheng Chou has 7 coauthors

Last update 2012-09-10 CET by the DBLP Team —

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