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| 6 | Pawel Chodowiec, Kris Gaj: Very Compact FPGA Implementation of the AES Algorithm. CHES 2003: 319-333 | |
| 5 | Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj: IPsec-Protected Transport of HDTV over IP. FPL 2003: 869-879 | |
| 4 | Kris Gaj, Pawel Chodowiec: Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays. CT-RSA 2001: 84-99 | |
| 3 | Pawel Chodowiec, Po Khuon, Kris Gaj: Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. FPGA 2001: 94-102 | |
| 2 | Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott: Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. ISC 2001: 220-234 | |
| 1 | Kris Gaj, Pawel Chodowiec: Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference 2000: 40-54 |
Selection of 6 from 7 records - Pawel Chodowiec has 10 coauthors
Copyright © 2009-12-04 by Michael Ley (ley@uni-trier.de)