dblp.uni-trier.dewww.dagstuhl.dewww.uni-trier.de

Kuo-Hsing Cheng (Selection)

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo


51Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng: Auto-calibration techniques in built-in jitter measurement circuit. DDECS 2012: 248-249
47Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo: All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS 2011: 486-489
44Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu: A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. VLSI Syst. 19(7): 1218-1228 (2011)
43Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong: Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. VLSI Syst. 19(8): 1325-1335 (2011)
41Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu: A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. on Circuits and Systems 58-II(8): 492-496 (2011)
39Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang: A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288
36Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng: 0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193

Selection of 7 from 51 records - Kuo-Hsing Cheng has 82 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page