Peter Celinski (Selection)

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6 Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis: Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI 2004: 127-134

4 Peter Celinski, Derek Abbott, Sorin Cotofana: Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. PATMOS 2004: 899-906

3 Peter Celinski, Derek Abbott, Sorin Dan Cotofana: Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ISCAS (5) 2003: 233-236

2 Peter Celinski, Sorin Cotofana, Derek Abbott: A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. IWANN (2) 2003: 73-80

1 Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López: Low depth carry lookahead addition using charge recycling threshold logic. ISCAS (1) 2002: 469-472

Selection of 5 from 6 records - Peter Celinski has 7 coauthors

6		Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis: Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI 2004: 127-134
4		Peter Celinski, Derek Abbott, Sorin Cotofana: Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. PATMOS 2004: 899-906
3		Peter Celinski, Derek Abbott, Sorin Dan Cotofana: Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ISCAS (5) 2003: 233-236
2		Peter Celinski, Sorin Cotofana, Derek Abbott: A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. IWANN (2) 2003: 73-80
1		Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López: Low depth carry lookahead addition using charge recycling threshold logic. ISCAS (1) 2002: 469-472