dblp.uni-trier.dewww.dagstuhl.dewww.uni-trier.de

Ruben W. Castelino (Selection)

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo


2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWilliam J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf: Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU Digital Technical Journal 7(1): 0- (1995)

Selection of 1 from 2 records - Ruben W. Castelino has 31 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page