Lars Bengtsson (Selection)

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13 Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191

10 Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563

7 Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson: Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878

6 Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors: DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. Applied Informatics 2003: 767-772

Selection of 4 from 16 records - Lars Bengtsson has 18 coauthors

13		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191
10		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563
7		Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson: Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878
6		Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors: DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. Applied Informatics 2003: 767-772