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| 8 | Shankar Balachandran, Dinesh Bhatia: Timing Aware Interconnect Prediction Models for FPGAs. FPL 2005: 167-172 | |
| 7 | Shankar Balachandran, Dinesh Bhatia: A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1054-1065 (2005) | |
| 6 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. VLSI Syst. 12(4): 381-385 (2004) | |
| 5 | Shankar Balachandran, Dinesh Bhatia: A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP 2003: 77-84 | |
| 4 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: On metrics for comparing routability estimation methods for FPGAs. DAC 2002: 70-75 | |
| 3 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: Rapid and Reliable Routability Estimation for FPGAs. FPL 2002: 242-252 | |
| 2 | Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia: On Routing Demand and Congestion Estimation for FPGAs. VLSI Design 2002: 639-646 | |
| 1 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL 2001: 37-47 |
Selection of 8 from 8 records - Shankar Balachandran has 2 coauthors
Copyright © 2009-12-01 by Michael Ley (ley@uni-trier.de)