Siamak Arya (Selection)

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4 Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162

3 Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180

Selection of 2 from 4 records - Siamak Arya has 3 coauthors

4		Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162
3		Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180