Ravishankar Arunachalam (Selection)

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4 Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731

3 Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: TACO: timing analysis with coupling. DAC 2000: 266-269

2 Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219

1 Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229

Selection of 4 from 7 records - Ravishankar Arunachalam has 10 coauthors

4		Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731
3		Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: TACO: timing analysis with coupling. DAC 2000: 266-269
2		Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219
1		Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229