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| 1 | Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229 |
Selection of 1 from 7 records - Ravishankar Arunachalam has 10 coauthors
Copyright © 2009-11-30 by Michael Ley (ley@uni-trier.de)