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| 12 |       | Qiang Wang, Subodh Gupta, Jason Helge Anderson: Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22 |
Selection of 1 from 13 records - Jason Helge Anderson has 16 coauthors
Copyright © 2009-12-05 by Michael Ley (ley@uni-trier.de)